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VHDLIntermediate

Testbench: Packet-length checker (VHDL)

Verify start, counting, early end and correct length.

Exercise objective

The DUT checks that a packet has the expected length.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT checks that a packet has the expected length.

Skills you will practice

  • Length
  • Error

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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