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VHDLIntermediate

Testbench: Baud tick generator (VHDL)

Verify division, reload and the exactly periodic pulse.

Exercise objective

The DUT produces a periodic tick from the system clock.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT produces a periodic tick from the system clock.

Skills you will practice

  • Period
  • Reload

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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