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VHDLIntermediate

Testbench: Simple dual-port memory (VHDL)

Verify writes, reads and independence of both ports.

Exercise objective

The DUT stores data and allows independent access through two ports.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT stores data and allows independent access through two ports.

Skills you will practice

  • Write
  • Read
  • Address

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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