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VHDLIntermediate

Testbench: Handshake controller (VHDL)

Verify valid/ready, data hold and transaction completion.

Exercise objective

The DUT manages a transaction when valid and ready are both asserted.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT manages a transaction when valid and ready are both asserted.

Skills you will practice

  • Valid
  • Ready
  • Completion

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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