Block Design
Zynq, AXI GPIO and Timer
Assemble a simplified Zynq system with reset, AXI interconnect, timer and two GPIO blocks.
Exercise objective
Assemble a simplified Zynq system with reset, AXI interconnect, timer and two GPIO blocks.
Prerequisites
- Read digital schematics and recognize clocks, resets and interfaces.
- Identify the blocks and interfaces needed for “Zynq, AXI GPIO and Timer”.
Skills you will practice
- Assemble a simplified Zynq system with reset, AXI interconnect, timer and two GPIO blocks.
- FPGA
- Block Design
- Vivado
- IP Integrator
Equipment and tools
- Browser-based Block Design editor.