Block Design
Zynq: Hierarchical PL Interrupts
Aggregate timer and GPIO interrupts in an AXI INTC before presenting them to the PS.
Exercise objective
Aggregate timer and GPIO interrupts in an AXI INTC before presenting them to the PS.
Prerequisites
- Read digital schematics and recognize clocks, resets and interfaces.
- Identify the blocks and interfaces needed for “Zynq: Hierarchical PL Interrupts”.
Skills you will practice
- Aggregate timer and GPIO interrupts in an AXI INTC before presenting them to the PS.
- Zynq
- Interruptions
- Vivado
- IP Integrator
Equipment and tools
- Browser-based Block Design editor.
- Zynq UltraScale+ MPSoC with PL IRQ enabled.