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Block Design

JTAG-to-AXI, BRAM and System ILA

Recreate AMD’s debug design: JTAG transactions to BRAM with AXI interface monitoring.

Exercise objective

Recreate AMD’s debug design: JTAG transactions to BRAM with AXI interface monitoring.

Prerequisites

  • Read digital schematics and recognize clocks, resets and interfaces.
  • Identify the blocks and interfaces needed for “JTAG-to-AXI, BRAM and System ILA”.

Skills you will practice

  • Recreate AMD’s debug design: JTAG transactions to BRAM with AXI interface monitoring.
  • Debug
  • JTAG
  • System ILA
  • IP Integrator

Equipment and tools

  • Browser-based Block Design editor.
  • AMD FPGA with JTAG access; 100 MHz.

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