Block Design
Multi-Clock AXI4-Stream Pipeline
Safely cross from a 100 MHz to a 150 MHz domain using Clock Converter and Data FIFO.
Exercise objective
Safely cross from a 100 MHz to a 150 MHz domain using Clock Converter and Data FIFO.
Prerequisites
- Read digital schematics and recognize clocks, resets and interfaces.
- Identify the blocks and interfaces needed for “Multi-Clock AXI4-Stream Pipeline”.
Skills you will practice
- Safely cross from a 100 MHz to a 150 MHz domain using Clock Converter and Data FIFO.
- AXI4-Stream
- CDC
- FIFO
- IP Integrator
Equipment and tools
- Browser-based Block Design editor.
- Any AMD target; 32-bit stream and two asynchronous clocks.