Block Design
MicroBlaze Executing from External DDR4
Connect MicroBlaze instruction and data buses to DDR4 through the UltraScale Memory IP.
Exercise objective
Design a MicroBlaze system using external DDR4 for instructions and data, then integrate a UART control peripheral.
Prerequisites
- Understand MicroBlaze instruction and data address spaces.
- Understand memory-mapped AXI interfaces, clock domains and reset domains.
Skills you will practice
- Organize processor access to external memory and peripherals.
- Define a coherent instruction and data memory map.
- Identify DDR4 interface constraints and calibration requirements.
Equipment and tools
- Browser-based Block Design editor.
- UltraScale/UltraScale+ FPGA with compatible DDR4 and known board pinout.