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Block Design

PCIe Endpoint with XDMA

Expose BRAM and AXI-Lite registers to a PCIe host through XDMA.

Exercise objective

Expose BRAM and AXI-Lite registers to a PCIe host through XDMA.

Prerequisites

  • Read digital schematics and recognize clocks, resets and interfaces.
  • Identify the blocks and interfaces needed for “PCIe Endpoint with XDMA”.

Skills you will practice

  • Expose BRAM and AXI-Lite registers to a PCIe host through XDMA.
  • PCIe
  • XDMA
  • BRAM
  • IP Integrator

Equipment and tools

  • Browser-based Block Design editor.
  • UltraScale/UltraScale+ board with compatible PCIe block, connector and supported reference clock.

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