Full SPI Master (Configurable mode)
Advanced01General Operation
The module implements a configurable SPI master supporting all 4 SPI modes (0 to 3) via CPOL and CPHA parameters derived from the g_MODE_SPI generic.
A transaction is triggered by i_spi_com_rqst. The module handles TX serialization (MSB first), RX deserialization, SPI clock generation and slave selection. TX and RX sizes are independent and configurable per transaction.
Generics:
| Generic | Type | Default | Description |
|---|---|---|---|
g_MODE_SPI | natural | 3 | SPI mode (0 to 3). Bits (1) and (0) of its 2-bit conversion give CPOL and CPHA |
g_CK_PER_HF_SPI | positive | 3 | System clock cycles per SPI clock half-period |
g_SHIFT_SPI_CLK | positive | 2 | Shift of o_sck relative to internal clock (in ticks). Must be < g_CK_PER_HF_SPI - 1 |
g_NB_SLAVE | positive | 1 | Number of SPI slaves |
g_DATA_2RC_SIZE | positive | 32 | Max receive data size (bits) |
g_DATA_2SD_SIZE | positive | 32 | Max transmit data size (bits) |
The SPI clock is derived from the system clock by division, with a half-period of g_CK_PER_HF_SPI cycles. The SPI mode determines clock polarity and phase. The output clock o_sck is shifted by g_SHIFT_SPI_CLK cycles relative to the internal clock.
The transaction starts on i_spi_com_rqst. The module selects the slave, serializes TX data, deserializes RX data and signals completion via o_data_rec_valid. During transmission, o_spi_busy='1'.
02Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 | System clock |
i_rst | Input | 1 | Active-high synchronous reset |
o_sck | Output | 1 | SPI clock (shifted by g_SHIFT_SPI_CLK ticks) |
o_ss_n | Output | g_NB_SLAVE | Active-low Slave Select |
i_miso | Input | 1 | Master In Slave Out |
o_mosi | Output | 1 | Master Out Slave In ('Z' when idle) |
o_data_rec_valid | Output | 1 | 1-cycle pulse: received data valid |
o_data_received | Output | g_DATA_2RC_SIZE | Received data |
o_frame_full_ok | Output | 1 | 1-cycle pulse: frame complete |
i_spi_com_rqst | Input | g_NB_SLAVE | Communication request (1 bit per slave, 1-cycle pulse) |
i_data_2send | Input | g_DATA_2SD_SIZE | Data to transmit |
i_data_2send_size | Input | f_log2(g_DATA_2SD_SIZE) | Number of bits to transmit |
i_data_2rec_size | Input | f_log2(g_DATA_2RC_SIZE) | Number of bits to receive |