Advanced VHDL exercises - Specification

Implement an interrupt generator: each IT vector stays active for g_MIN_WIDTH_PULSE cycles then is reported in the status register.

Implement a generic AXI4-Lite master capable of performing read and write accesses on an AXI4-Lite bus.

Implement a generic AXI4-Lite slave with simplified register interface.

Implement a simple AXI4 master managing the three write channels: Write Address (AW), Write Data (W) and Write Response (B).

Implement a 16-bit accumulator-based mini processor: ALU, PC/IR/ACC/R registers, control FSM, and top-level assembly. 14 instructions covered.

Implement a hardware SHA-256 core on a 512-bit block: logical functions, message schedule shift register, compression unit and top-level FSM.

Implement a successive-approximation conversion FSMD to drive an internal DAC and read a comparator.

Implement a simplified IEEE-754 single-precision multiplier with mantissa/exponent split.

Build a simulation ROM from Intel HEX records provided by the project.

Develop a functional µ-law compression model for a normalized real-valued signal.

Model a simple DDR output from two opposite-edge registers.

Build a decimal seconds/tenths stopwatch driven by an external tick.

Implement a small 8-bit FIFO between two clock domains.

Implement an integer IIR biquad cell with fixed coefficients.

Average four samples then output one decimated sample.

Arbitrate two masters onto a single memory port.

Sort four 4-bit values with a comparator network inspired by bubble sort.

Merge two already-sorted pairs into four sorted outputs.

Compute the median of five 4-bit values.

Implement a 3-tap 1D convolution with fixed coefficients `1,2,1`.

Transpose a 2x2 byte matrix packed into 32 bits.

Measure the longest `+1` run in four already-sorted values.

Compute one neuron with a single multiply-accumulate unit reused across several cycles.

Compute two fully connected neurons in parallel from four signed inputs.

Implement signed multiplication by recoding multiplier transitions.

Compute a sum or difference reduced to the range zero through m minus one.

Compute x times y modulo m over eight cycles without a combinational multiplier.

Compute a modular product in the Montgomery domain with eight binary iterations.

Divide two unsigned integers with eight steps alternating subtraction and addition.