library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.report_sim_pkg.all; entity tb_top_level is end entity tb_top_level; architecture sim of tb_top_level is constant c_CLK_PER : time := 10 ns; signal s_clk : std_logic := '0'; signal s_we : std_logic := '0'; signal s_addr : std_logic_vector(7 downto 0) := (others => '0'); signal s_data : std_logic_vector(7 downto 0) := (others => '0'); signal s_qout : std_logic_vector(7 downto 0); begin s_clk <= not s_clk after c_CLK_PER / 2; DUT : entity work.ram_256x8 port map ( i_clk => s_clk, i_we => s_we, i_addr => s_addr, i_data => s_data, o_data => s_qout ); P_STIM : process variable v_pass : integer := 0; variable v_fail : integer := 0; variable v_count : integer := 0; begin ---------------------------------------------------------------- -- Write x"AA" to address 0 ---------------------------------------------------------------- s_we <= '1'; s_addr <= x"00"; s_data <= x"AA"; wait until rising_edge(s_clk); ---------------------------------------------------------------- -- Write x"55" to address 1 ---------------------------------------------------------------- s_addr <= x"01"; s_data <= x"55"; wait until rising_edge(s_clk); -- Stop writing s_we <= '0'; ---------------------------------------------------------------- -- Read back from address 0 (synchronous: set addr, wait 1 cycle) ---------------------------------------------------------------- s_addr <= x"00"; wait until rising_edge(s_clk); wait for 1 ns; check_output(s_qout, x"AA", "READ_ADDR0", v_pass, v_fail, v_count); ---------------------------------------------------------------- -- Read back from address 1 ---------------------------------------------------------------- s_addr <= x"01"; wait until rising_edge(s_clk); wait for 1 ns; check_output(s_qout, x"55", "READ_ADDR1", v_pass, v_fail, v_count); ---------------------------------------------------------------- -- Write x"FF" to address 2, then read it back ---------------------------------------------------------------- s_we <= '1'; s_addr <= x"02"; s_data <= x"FF"; wait until rising_edge(s_clk); s_we <= '0'; -- Read back: address already set to 0x02 wait until rising_edge(s_clk); wait for 1 ns; check_output(s_qout, x"FF", "READ_ADDR2", v_pass, v_fail, v_count); ---------------------------------------------------------------- -- Verify address 0 still holds x"AA" ---------------------------------------------------------------- s_addr <= x"00"; wait until rising_edge(s_clk); wait for 1 ns; check_output(s_qout, x"AA", "REREAD_ADDR0", v_pass, v_fail, v_count); ---------------------------------------------------------------- -- Done ---------------------------------------------------------------- final_report("tb_ram_256x8", v_pass, v_fail); wait; end process P_STIM; end architecture sim;

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_we`	Input	1 bit	Write enable
`i_addr`	Input	8 bits	Address (0 to 255)
`i_data`	Input	8 bits	Data to write
`o_data`	Output	8 bits	Data read

Single-Port RAM 256x8

Single-Port RAM 256x8