Beginner VHDL exercises - Hardware → Simulation

Wire the provided components into a structural TOP_LEVEL.

N-bit Comparator

Implement a parametric comparator capable of comparing two unsigned values.

Double Flip-Flop Synchronizer

Implement a two-stage synchronizer to safely transfer an asynchronous signal into a clock domain.

TelecomAerospace

Rising Edge Detector

Implement a rising edge detector that generates a one-clock-cycle pulse on each 0→1 transition of the input signal.

Falling Edge Detector

Implement a falling edge detector that generates a one-clock-cycle pulse on each 1→0 transition of the input signal.

4:1 Mux from 2:1 Muxes

VHDL

Build a 4-to-1 multiplexer by instantiating three 2-to-1 multiplexers from the package.

Complete Falling Edge Detector

2-to-4 Decoder

VHDL

Implement a 2-to-4 binary decoder with active-high one-hot output.

Complete 4:1 Mux from 2:1 Muxes

4-to-2 Priority Encoder

VHDL

Implement a 4-to-2 priority encoder: the binary output gives the index of the highest active bit in `i_d`.

Complete 2-to-4 Decoder

Half Subtractor

VHDL

Implement a 1-bit half subtractor producing the difference and the outgoing borrow.

Complete 4-to-2 Priority Encoder

8-bit Parity Detector (XOR Tree)

VHDL

Compute the even parity of an 8-bit word using a 3-level XOR tree.

Complete Half Subtractor

4-bit Ripple-Carry Adder

VHDL

Build a 4-bit adder by chaining four 1-bit full-adders provided in the package.

Complete 8-bit Parity Detector (XOR Tree)

D Flip-flop with Async Set/Reset

VHDL

Implement a D flip-flop with asynchronous set and reset, both priority over the clock.

Complete 4-bit Ripple-Carry Adder

T Flip-flop from D Flip-flop

VHDL

Build a T flip-flop by wiring a D flip-flop with an XOR gate.

Complete D Flip-flop with Async Set/Reset

3-bit Asynchronous (Ripple) Counter

VHDL

Build a 3-bit ripple counter by chaining three T flip-flops from the package.

Complete T Flip-flop from D Flip-flop

Divide-by-4 Frequency Divider

VHDL

Cascade two T flip-flops to produce a clock four times slower than `i_clk`.

Complete 3-bit Asynchronous (Ripple) Counter

Serial-to-Parallel Converter

VHDL

Code a parameterized shift register using a `generate` structure.