Hardware → Simulation

Beginner

Analyze the schematic and write the matching VHDL. GHDL simulation validates your code.

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TOP_LEVEL — BCD 7-Segment Counter

Code the three components and wire them into a structural TOP_LEVEL.

N-bit Comparator

Implement a parametric comparator capable of comparing two unsigned values.

Locked

Double Flip-Flop Synchronizer

Implement a two-stage synchronizer to safely transfer an asynchronous signal into a clock domain.

Locked

Rising Edge Detector

Implement a rising edge detector that generates a one-clock-cycle pulse on each 0→1 transition of the input signal.

Locked

Falling Edge Detector

Implement a falling edge detector that generates a one-clock-cycle pulse on each 1→0 transition of the input signal.

Locked