Specification

Implement an SPI master (mode 0: CPOL=0, CPHA=0) capable of transmitting and receiving a byte over an SPI bus.

Implement an SPI master in mode 0 (CPOL=0, CPHA=0) capable of transferring 8 bits serially.

Implement a synchronous BCD counter that counts from 0 to 9 then wraps to 0, with active-low asynchronous reset and enable input.

Implement a generic clock divider that divides the input frequency by 2×-_HALF, with asynchronous reset.

Implement a D flip-flop with enable and active-high asynchronous reset. The flip-flop stores i_d on the rising edge only if i_en is active.

Implement a 4-bit serial shift register (SISO) with asynchronous reset. Bits shift right on each rising edge.

Implement a Mealy state machine that detects the binary sequence «101» on a serial input, with overlap handling.

Implement a combinational ALU performing 4 operations on two 8-bit operands: addition, subtraction, AND, and OR, with carry flag.

Implement a transparent latch to understand this classic FPGA pitfall. When enable is high, output follows input; when enable is low, output holds its value.

Implement an 8-bit loadable shift register combining parallel load and left shift, with load taking priority.

Implement a pulse stretcher that extends a single-cycle signal into an output active for G_CYCLES clock cycles.

Implement a safety watchdog timer: a counter decrements continuously and triggers a timeout if no i_kick signal is received in time.

Implement a 3-state FSM controller (OFF, BLINK, ON) that drives an LED with blinking. Each button press advances the sequence.

Implement a PWM generator with a sequential counter and a combinational output controlled by the duty cycle.

Implement an 8-bit Linear Feedback Shift Register (LFSR) with seed loading and combinational feedback output.

Implement a 4-sample moving average filter with a sequential shift register and combinational average computation.

Implement an N-bit parallel register with enable and combinational update detection.

Implement a two flip-flop CDC synchronizer with combinational rising and falling edge detection.

Implement a synchronous CRC-16 calculator, bit by bit, with the CCITT polynomial and a combinational output of the CRC register.

Implement the first two phases of an I2C master: START condition and sending the 7-bit address + R/W bit via a 5-state FSM.

Implement a 7-segment decoder that converts a BCD digit (0-9) into 7 signals to light the correct display segments, with enable.

Implement a top level that instantiates a BCD counter and a 7-segment decoder, correctly wiring internal signals and external ports.

Design a 1-bit full adder with carry-in and carry-out. This block is the fundamental building block of any arithmetic unit.

Design a purely combinational 4-to-1 multiplexer. The 2-bit selector chooses which of the 4 inputs is forwarded to the output.

Design a 2-to-4 binary decoder with an enable signal. The output is a one-hot code corresponding to the selector value when the decoder is active.

Design an 8-bit parity checker. The output indicates whether the number of 1-bits in the input is odd (parity = 1) or even (parity = 0).

Design a 4-bit combinational comparator that compares two unsigned numbers and indicates whether the first is greater than, equal to, or less than the second.

Design a 4-bit combinational multiplier that computes the product of two unsigned numbers on an 8-bit output.

Design a combinational converter that transforms an 8-bit BCD (Binary-Coded Decimal) number into its 7-bit binary value.

Design a two-input AND logic gate. This is the fundamental building block of all combinational logic.

Design a two-input OR logic gate. The output is active when at least one input is '1'.

Design a logic inverter. The output is the complement of the input.

Design a two-input NAND logic gate. This is the universal gate: any logic function can be built using NAND gates.

Design a two-input NOR logic gate. Like NAND, it is a universal gate.

Design a two-input XOR (exclusive OR) logic gate. Used in adders, parity detection and encryption.

Design a two-input XNOR (equivalence) logic gate. The output is active when both inputs are the same.

Design a purely combinational 2-to-1 multiplexer. The selector chooses which of the 2 inputs is forwarded to the output.

Design a purely combinational 8-to-1 multiplexer. The 3-bit selector chooses which of the 8 inputs is forwarded to the output.

Design a 1-to-2 demultiplexer. The input is routed to one of the two outputs based on the selector.

Design a 1-to-4 demultiplexer. The input is routed to one of the four outputs based on the 2-bit selector.

Design a 3-to-8 binary decoder with enable signal. The output is a one-hot code corresponding to the selector value.

Design a 4-bit binary to Gray code converter. Gray code is used in communications because only one bit changes between consecutive values.

Design a 4-bit Gray code to binary converter. Inverse operation of the binary to Gray converter.

Design a half adder that adds two bits without carry-in.

Design a 4-bit combinational subtractor that computes the difference of two unsigned numbers with borrow indication.

Implement a JK flip-flop with active-high asynchronous reset. The JK flip-flop is the most versatile: it can hold, set, reset, or toggle its output.

Implement a T (Toggle) flip-flop with active-high asynchronous reset. When T='1', the output toggles on each rising edge.

Implement a synchronous SR flip-flop with active-high asynchronous reset. S sets the output to '1', R resets it to '0'.

Implement a 4-bit register with enable and active-high asynchronous reset.

Implement a 4-bit left shift register with serial input and asynchronous reset.

Implement a 4-bit serial-in parallel-out (SIPO) shift register with asynchronous reset. Bits enter serially and are available in parallel.

Implement a 4-bit synchronous up counter with enable and asynchronous reset.

Implement a 4-bit synchronous down counter with enable and asynchronous reset. Reset initializes to maximum value (15).

Implement a 4-bit ring counter with asynchronous reset. A single '1' bit circulates through the register.