AXI4-Lite Slave

Advanced

00:00

01General Operation

The module translates AXI4-Lite transactions into simplified register access via o_slv_go, o_slv_rnw, o_slv_addr, o_slv_wdata. An external backend performs reads/writes and returns status. The module handles AXI4-Lite handshakes on all 5 channels.

Generics: G_AXI_ADDR_WIDTH (default 32), G_AXI_DATA_WIDTH (default 32), G_AXI_ID_WIDTH (default 12)

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_rst`	Input	1 bit	Synchronous active-high reset
`i_axi_awid`	Input	G_AXI_ID_WIDTH bits	Write ID
`i_awaddr`	Input	G_AXI_ADDR_WIDTH bits	Write address
`i_awvalid`	Input	1 bit	AW Valid
`o_awready`	Output	1 bit	AW Ready
`i_wdata`	Input	G_AXI_DATA_WIDTH bits	Write data
`i_wvalid`	Input	1 bit	W Valid
`o_wready`	Output	1 bit	W Ready
`o_axi_bid`	Output	G_AXI_ID_WIDTH bits	Write response ID
`o_bresp`	Output	2 bits	Write response
`o_bvalid`	Output	1 bit	B Valid
`i_bready`	Input	1 bit	B Ready
`i_araddr`	Input	G_AXI_ADDR_WIDTH bits	Read address
`i_arvalid`	Input	1 bit	AR Valid
`o_arready`	Output	1 bit	AR Ready
`o_rdata`	Output	G_AXI_DATA_WIDTH bits	Read data
`o_rresp`	Output	2 bits	Read response
`o_rvalid`	Output	1 bit	R Valid
`i_rready`	Input	1 bit	R Ready
`o_slv_go`	Output	1 bit	Register access trigger
`o_slv_rnw`	Output	1 bit	'1' = read
`o_slv_addr`	Output	G_AXI_ADDR_WIDTH bits	Register address
`o_slv_wdata`	Output	G_AXI_DATA_WIDTH bits	Write data
`i_slv_rdata`	Input	G_AXI_DATA_WIDTH bits	Read data
`i_slv_done`	Input	1 bit	Register access done
`i_slv_status`	Input	2 bits	Status (OKAY/SLVERR/DECERR)

← AXI4-Lite Master AXI4 Master — Write Channels →

Chargement…