Dual Edge Flip Flop

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Specification

01General Operation

The module separates rising-edge and falling-edge capture, then multiplexes according to the clock.

Behaviour

Rising edge: capture i_d_rise.
Falling edge: capture i_d_fall.
o_q follows the rising register when i_clk=1, and the falling register when i_clk=0.

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_reset`	Input	1 bit	Active-high asynchronous reset
`i_d_rise`	Input	1 bit	Input d rise
`i_d_fall`	Input	1 bit	Input d fall
`o_q`	Output	1 bit	Output q

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