SPI Master Mode 0
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01General Operation
The module implements an SPI master in mode 0 (CPOL=0, CPHA=0) with a configurable clock divider. A transaction starts on command and transfers data serially, MSB first. The module manages Chip Select and signals availability.
Reset is synchronous and active-high.
Generics:
g_clk_div: integer (default 4) — Number of system clock cycles per SCK half-period. Withg_clk_div=4, SCK toggles every 4 cycles → SCK frequency = Fclk/8.
- State machine for protocol management
- SCK frequency is set by the
g_clk_divgeneric
02Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_rst | Input | 1 bit | Synchronous reset |
i_start | Input | 1 bit | Start transaction |
i_data | Input | 8 bits | Data to transmit |
i_miso | Input | 1 bit | Master In Slave Out |
o_data | Output | 8 bits | Received data |
o_done | Output | 1 bit | '1' during DONE state |
o_sck | Output | 1 bit | Generated SPI clock |
o_mosi | Output | 1 bit | Master Out Slave In |
o_cs_n | Output | 1 bit | Active-low Chip Select |