8-bit SPI Master
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01General Operation
The SPI master generates the SCK clock by dividing the system clock (configurable via generic). A transaction starts on command and sends/receives a configurable number of bits in mode 0 (CPOL=0, CPHA=0). The module manages Slave Select and signals when busy.
Reset is synchronous and active-high.
- SCK frequency is set by the
g_CLK_DIVgeneric - Data is transmitted MSB first
02Interface
Generics:
g_CLK_DIV: positive (default 4) — System cycles per SCK half-periodg_DATA_WIDTH: positive (default 8) — Bits per frame
Ports:
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_rst | Input | 1 bit | Synchronous reset |
i_start | Input | 1 bit | Start transaction |
i_data | Input | g_DATA_WIDTH | Data to transmit |
o_sck | Output | 1 bit | Generated SPI clock |
o_ss_n | Output | 1 bit | Active-low Slave Select |
o_mosi | Output | 1 bit | Master Out Slave In |
i_miso | Input | 1 bit | Master In Slave Out |
o_data | Output | g_DATA_WIDTH | Received data |
o_data_valid | Output | 1 bit | Data valid pulse |
o_busy | Output | 1 bit | Transaction in progress |