library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.report_sim_pkg.all; entity tb_top_level is end entity tb_top_level; architecture sim of tb_top_level is constant c_CLK_PER : time := 10 ns; signal s_clk : std_logic := '0'; signal s_reset : std_logic := '1'; signal s_en : std_logic := '0'; signal s_d : std_logic := '0'; signal s_q : std_logic; begin s_clk <= not s_clk after c_CLK_PER / 2; DUT : entity work.bascule_d port map ( i_clk => s_clk, i_reset => s_reset, i_en => s_en, i_d => s_d, o_q => s_q ); P_STIM : process variable v_pass : integer := 0; variable v_fail : integer := 0; variable v_count : integer := 0; begin -- Reset s_reset <= '1'; wait for 50 ns; check_output(s_q, '0', "Q_RESET", v_pass, v_fail, v_count); s_reset <= '0'; wait for 20 ns; -- Store '1' with enable s_en <= '1'; s_d <= '1'; wait until rising_edge(s_clk); wait for 1 ns; check_output(s_q, '1', "Q_STORE_1", v_pass, v_fail, v_count); -- Store '0' with enable s_d <= '0'; wait until rising_edge(s_clk); wait for 1 ns; check_output(s_q, '0', "Q_STORE_0", v_pass, v_fail, v_count); -- Hold value without enable s_en <= '0'; s_d <= '1'; wait until rising_edge(s_clk); wait for 1 ns; check_output(s_q, '0', "Q_HOLD", v_pass, v_fail, v_count); -- Re-enable and store s_en <= '1'; wait until rising_edge(s_clk); wait for 1 ns; check_output(s_q, '1', "Q_REENABLE", v_pass, v_fail, v_count); -- Async reset while running s_reset <= '1'; wait for 5 ns; check_output(s_q, '0', "Q_ASYNC_RST", v_pass, v_fail, v_count); final_report("tb_bascule_d", v_pass, v_fail); wait; end process P_STIM; end architecture sim;

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_reset`	Input	1 bit	Active-high async reset
`i_en`	Input	1 bit	Enable
`i_d`	Input	1 bit	Data input
`o_q`	Output	1 bit	Stored data

D Flip-Flop with Enable

D Flip-Flop with Enable