Chargement…
Chargement…
Parallel register of configurable width (g_width bits). Stores input data on the rising clock edge when enable is active. The o_updated output pulses for one cycle after each write.
Reset is asynchronous and active-high.
g_width (default 8)| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_en | Input | 1 bit | Write enable |
i_data | Input | g_width bits | Input data |
o_q | Output | g_width bits | Register value |
o_updated | Output | 1 bit | Update pulse |