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The CDC synchronizer transfers a signal between two independent clock domains using a two flip-flop chain. It outputs the synchronized signal along with single-cycle pulses detecting rising and falling edges.
Reset is asynchronous and active-high.
ASYNC_REG attribute| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk_dst | Input | 1 bit | Destination domain clock |
i_reset_dst | Input | 1 bit | Active-high async reset |
i_data_src | Input | 1 bit | Source domain signal |
o_data_dst | Output | 1 bit | Synchronized signal |
o_re_detected | Output | 1 bit | Rising edge pulse |
o_fe_detected | Output | 1 bit | Falling edge pulse |