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JK Flip-Flop

Beginner

00:00

01General Operation

On rising edge of i_clk:

J=0, K=0: hold (no change)
J=0, K=1: reset (o_q <= '0')
J=1, K=0: set (o_q <= '1')
J=1, K=1: toggle (o_q <= not o_q)

Asynchronous reset forces output to '0'.

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_reset`	Input	1 bit	Active-high async reset
`i_j`	Input	1 bit	J input (set)
`i_k`	Input	1 bit	K input (reset)
`o_q`	Output	1 bit	Flip-flop output

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