Chargement…
Chargement…
4-bit ring counter: a single '1' walks through the register by left-rotation.
Behaviour:
i_reset='1'): o_q ← "0001".i_clk: left rotation, the leaving MSB re-enters through the LSB.Generated sequence:
0001 → 0010 → 0100 → 1000 → 0001 → ...
*Asynchronous active-high reset.*
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
o_q | Output | 4 bits | Counter output |