Specification

Implement a simple AXI4 master managing the two read channels: Read Address (AR) and Read Data (R).

Implement an AXI-Lite slave with three 32-bit read/write registers, managed by two independent state machines.

Implement a 3-process state machine for a pedestrian light with integrated timer and per-state duration management.

Implement a 3-process Moore state machine that cycles 4 LEDs in sequence on command.

Implement an N-bit ripple carry adder using only logical operators, without any arithmetic library.

Implement a generic bidirectional counter with parallel load, enable, and asynchronous reset.

Implement a debouncer circuit with configurable stabilization time via generics.

Implement an 8-to-3 combinational priority encoder that encodes the position of the highest-priority active bit.

Implement a 4-bit Johnson counter with synchronous reset. The counter goes through a sequence of 8 states before returning to its initial state.

Implement an 8-bit barrel shifter performing a logical left shift in 3 combinational stages (shift-by-4, shift-by-2, shift-by-1).

Implement a W1C register: bits are set via i_set_en and cleared by writing 1 via i_clr_en.

Generate a 1µs periodic pulse from a system clock with known period.

Implement a generic synchronous N-bit counter with enable, asynchronous reset and overflow indication.

Implement an 8-bit combinational comparator that compares two unsigned numbers and indicates their relationship.

Implement a 4-bit combinational block selectable between addition and subtraction via a control signal.

Implement a generic cascadable comparator with cascade inputs for connecting multiple stages.

Implement an 8-bit register with parallel load enable and asynchronous reset.

Implement a 4-bit shift register that can shift left, shift right, parallel load, or hold its value.

Implement an 8-word by 4-bit read-only memory (ROM), purely combinational.

Implement a 16-word by 4-bit ROM using a VHDL constant array.

Implement an 8-word by 4-bit RAM with synchronous write and asynchronous read.

Implement a 16-word by 4-bit RAM with synchronous write and asynchronous read.

Implement an 8-deep, 8-bit LIFO stack with push, pop, and empty/full flags.

Implement an 8-word by 8-bit dual-port RAM: independent write and read ports.

Implement a 4-register, 8-bit register file with 1 write port and 2 read ports.

Implement a 4-bit Carry Lookahead Adder (CLA).

Implement an 8-bit CLA adder by cascading two 4-bit CLA blocks.

Implement a 4-bit, 2-stage barrel shifter that can logically shift left by 0 to 3 positions.

Implement an adder for a simplified float format: 1 sign bit, 3 exponent bits (bias 3), 4 mantissa bits (implicit 1.xxxx).

Implement a multiplier for the same simplified float format: 1 sign bit, 3 exponent bits (bias 3), 4 mantissa bits (implicit 1).

Implement an even parity generator: generates a parity bit for 7 data bits, and verifies an 8-bit word (7 data + 1 parity).

Implement a population counter: count the number of '1' bits in an 8-bit vector.

Implement a priority multiplexer: 4 data channels of 4 bits with request bits. The highest-priority active channel is selected.

Implement a 4-phase handshake synchronizer to transfer a data bus between two independent clock domains.