Intermediate VHDL exercises - Specification

Implement an N-bit ripple carry adder using only logical operators, without any arithmetic library.

Implement a generic bidirectional counter with parallel load, enable, and asynchronous reset.

Implement a debouncer circuit with configurable stabilization time via generics.

Implement an 8-to-3 combinational priority encoder that encodes the position of the highest-priority active bit.

Implement a 4-bit Johnson counter with synchronous reset. The counter goes through a sequence of 8 states before returning to its initial state.

Implement an 8-bit barrel shifter performing a logical left shift in 3 combinational stages (shift-by-4, shift-by-2, shift-by-1).

Implement a W1C register: bits are set via i_set_en and cleared by writing 1 via i_clr_en.

Generate a 1µs periodic pulse from a system clock with known period.

Implement a generic synchronous N-bit counter with enable, asynchronous reset and overflow indication.

Implement an 8-bit combinational comparator that compares two unsigned numbers and indicates their relationship.

Implement a 4-bit combinational block selectable between addition and subtraction via a control signal.

Implement a generic cascadable comparator with cascade inputs for connecting multiple stages.

Implement an 8-bit register with parallel load enable and asynchronous reset.

Implement a 4-bit shift register that can shift left, shift right, parallel load, or hold its value.

Implement an 8-word by 4-bit read-only memory (ROM), purely combinational.

Implement a 16-word by 4-bit ROM using a VHDL constant array.

Implement an 8-word by 4-bit RAM with synchronous write and asynchronous read.

Implement a 16-word by 4-bit RAM with synchronous write and asynchronous read.

Implement an 8-deep, 8-bit LIFO stack with push, pop, and empty/full flags.

Implement an 8-word by 8-bit dual-port RAM: independent write and read ports.

Implement a 4-register, 8-bit register file with 1 write port and 2 read ports.

Implement a 4-bit Carry Lookahead Adder (CLA).

Implement an 8-bit CLA adder by cascading two 4-bit CLA blocks.

Implement a 4-bit, 2-stage barrel shifter that can logically shift left by 0 to 3 positions.

Implement an adder for a simplified float format: 1 sign bit, 3 exponent bits (bias 3), 4 mantissa bits (implicit 1.xxxx).

Implement a multiplier for the same simplified float format: 1 sign bit, 3 exponent bits (bias 3), 4 mantissa bits (implicit 1).

Implement an even parity generator: generates a parity bit for 7 data bits, and verifies an 8-bit word (7 data + 1 parity).

Implement a population counter: count the number of '1' bits in an 8-bit vector.

Implement a priority multiplexer: 4 data channels of 4 bits with request bits. The highest-priority active channel is selected.

Implement a 4-phase handshake synchronizer to transfer a data bus between two independent clock domains.

Implement a 5-tap direct-form FIR low-pass filter with line buffer and fixed coefficients.

Transform a 5x5 combinational multiplier into a 4-stage pipelined architecture.

Decode a Hamming (7,4) word, compute the syndrome and correct one single-bit error.

Implement a Parallel-In Serial-Out register with parallel load and controlled shifting.

Design a synchronous counter that cycles through states 0 to 5 with enable and terminal-count pulse.

Create a `time_of_day_pkg` package, a `record` type and a reusable time-of-day counter.

Implement a combinational arbiter that grants the bus to the requester with the lowest numeric priority.

Compare two signed-magnitude numbers without treating them as two's-complement values.

Code a bit-order reverser compatible with vectors of different sizes and directions.

Convert an 8-bit binary word into three BCD digits.

Implement a 4-bit counter that exposes its value as Gray code.

Count consecutive zeros starting at the most significant bit.

Compute the difference between two consecutive valid samples.

Linearly interpolate between four fixed table points.

Control four 4-bit counters with select, increment, and clear.

Accumulate four histogram bins from 2-bit samples.

Generate a read-then-write sequence to copy four words.

Accumulate signed values into four scratchpad locations.

Determine whether a 4-bit value is prime.

Output the maximum of the last four valid samples.

Compute `n!` for a 3-bit input from 0 to 5.

Check whether four nibbles form a palindrome sequence.

Find whether any pair among four values reaches a target.

Compress a 4-bit stream by emitting symbol and run length on changes.

Detect a local maximum in an 8-bit sample stream.

Search a target in four sorted ascending values.

Compute the dot product of two four-element 4-bit vectors.

Insert a stream of four values into an internal sorted array.

Return the most frequent value among four 4-bit values.

Detect an increasing run followed by a decreasing run in four values.

Split a 14-byte Ethernet II header into its main fields.

Compute the one’s-complement checksum over ten 16-bit IPv4 header words.

Detect an IPv4/Ethernet ARP request targeting the local address.

Implement unsigned 8x8 multiply-accumulate.

Implement 8-bit integer division in eight steps, with quotient, remainder, and divide-by-zero detection.

Measure the exact number of system cycles between two rising edges of a synchronized external signal.

Approximate a sigmoid function from a signed Q4.4 input with a 16-level lookup table.

Add four unsigned words with one adder reused over four cycles.

Compress four operands without propagating carry every cycle, then perform one final addition.

Compute an 8 by 8-bit signed product with additions and shifts over eight cycles.

Smooth large changes while passing small variations in a pixel stream.