Synchronous Modulo-6 Counter

Intermediate

00:00

01General Operation

The counter advances only when i_en='1'. After state 5, it returns to 0. o_tick is '1' during the cycle where the counter is at 5 and i_en='1', allowing another counter to be chained.

Behaviour

synchronous active-high reset;
hold value when i_en='0';
sequence: 0, 1, 2, 3, 4, 5, 0.

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	Clock
`i_rst`	Input	1 bit	Synchronous active-high reset
`i_en`	Input	1 bit	Count enable
`o_count`	Output	3 bits	Current value 0 to 5
`o_tick`	Output	1 bit	Terminal-count pulse

← 4-Bit PISO Register

Chargement…