Chargement…
Chargement…
The module reverses the logical bit order from i_data to o_data. Both ports are unconstrained: the size is fixed at instantiation.
Behaviour
o_data must have the same length as i_data;downto and to;'range, 'length, 'ascending, 'left) instead of hardcoded sizes;| Signal | Direction | Type | Description |
|---|---|---|---|
i_data | Input | unconstrained std_logic_vector | Vector to reverse |
o_data | Output | unconstrained std_logic_vector | Reversed vector |