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Memory Copy Controller

Intermediate

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Specification

01General Operation

The controller emits eight transactions: source read then destination write for each word.

Behaviour

i_start launches a four-word copy.
A read accepted by i_ready stores i_mem_rdata.
The following write presents that data on o_mem_wdata.
o_busy stays high during the copy and o_done pulses at the end.

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_reset`	Input	1 bit	Active-high asynchronous reset
`i_start`	Input	1 bit	Starts the copy
`i_src_base`	Input	8 bits	First source address
`i_dst_base`	Input	8 bits	First destination address
`i_ready`	Input	1 bit	Memory transaction accepted
`i_mem_rdata`	Input	8 bits	Memory read data
`o_mem_addr`	Output	8 bits	Current memory address
`o_mem_we`	Output	1 bit	Write enable
`o_mem_valid`	Output	1 bit	Valid memory transaction
`o_mem_wdata`	Output	8 bits	Memory write data
`o_busy`	Output	1 bit	Copy in progress
`o_done`	Output	1 bit	Copy complete

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