Signed Sequential Multiplier

When accepting i_start, store the result sign and convert both inputs to magnitudes. For eight cycles, add the shifted multiplicand when the multiplier least-significant bit is 1, shift the multiplicand left and multiplier right. Apply the sign after the final addition.

Both inputs are 8-bit two's-complement values. The product is 16-bit two's complement. o_busy remains active during calculation and o_done is a one-cycle pulse. Reset is synchronous active high.

The testbench covers sign combinations, zero, -128 * 127, and -128 * -128. The magnitude of -128 must be preserved without intermediate overflow.