Chargement…
Chargement…
Start from software code and compare it with several RTL schematics. The goal is to choose the architecture that exactly preserves priorities, conditions, and registers.
0/27 exercises completed
Find the correct schematic - PAL Chip-select Decoder
VerilogMatch partial decoding of the four most-significant address bits to its logic diagram.
Complete the 5th SW→HW exercise
Find the correct schematic - Two-digit BCD Adder
VerilogIdentify the decimal adder datapath that corrects each digit when its sum exceeds nine.
Complete the 5th SW→HW exercise
Find the correct schematic - Dual-priority Encoder
VerilogInfer the network that successively extracts the two lowest-index active requests.
Complete the 5th SW→HW exercise
Find the correct schematic - Four-digit BCD Sanitizer
VerilogAnalyze the Verilog code for four-digit bcd sanitizer.
Complete the 5th SW→HW exercise
Find the correct schematic - Eight-bit Thermometer Decoder
VerilogAnalyze the Verilog code for eight-bit thermometer decoder.
Complete the 5th SW→HW exercise
Find the correct schematic - Eight-bit Saturating Adder
VerilogAnalyze the Verilog code for eight-bit saturating adder.
Complete the 5th SW→HW exercise
Find the correct schematic - BCD Magnitude Comparator
VerilogAnalyze the Verilog code for bcd magnitude comparator.
Complete the 5th SW→HW exercise
Find the correct schematic - Five-input Majority Voter
VerilogAnalyze the Verilog code for five-input majority voter.
Complete the 5th SW→HW exercise
Find the correct schematic - One-hot Vector Analyzer
VerilogAnalyze the Verilog code for one-hot vector analyzer.
Complete the 5th SW→HW exercise
Find the correct schematic - LFSR Stream Cipher
VerilogIdentify the feedback loop and output XOR of a synchronous stream cipher.
Find the correct schematic - Ones-complement Checksum
VerilogFind the accumulator that folds the most-significant carry before complementing the result.
Find the correct schematic - Period Counter
VerilogReconstruct edge detection and capture of a cycle counter between two events.
Find the correct schematic - PRBS Sequence Checker
VerilogAnalyze the Verilog code for prbs sequence checker.
Find the correct schematic - SRAM Byte-lane Mapper
VerilogAnalyze the Verilog code for sram byte-lane mapper.
Find the correct schematic - PS/2 Frame Validator
VerilogAnalyze the Verilog code for ps/2 frame validator.
Complete the 5th SW→HW exercise
Find the correct schematic - Reciprocal Frequency Estimator
VerilogAnalyze the Verilog code for reciprocal frequency estimator.
Complete the 5th SW→HW exercise
Find the correct schematic - Windowed Watchdog Decision
VerilogAnalyze the Verilog code for windowed watchdog decision.
Complete the 5th SW→HW exercise
Find the correct schematic - Eight-request Rotating Arbiter
VerilogAnalyze the Verilog code for eight-request rotating arbiter.
Complete the 5th SW→HW exercise
Find the correct schematic - Asynchronous SRAM Controller
VerilogIdentify the state machine that stabilizes address and data around an SRAM access cycle.
Find the correct schematic - Burst DMA Controller
VerilogTrace the read/write alternation and address updates of a DMA transfer.
Find the correct schematic - VeSPA Hazard Unit
VerilogIdentify forwarding comparators and load-use hazard detection in a pipeline.
Find the correct schematic - DRAM Refresh Decision Unit
VerilogAnalyze the Verilog code for dram refresh decision unit.
Find the correct schematic - Fast-page DRAM Command
VerilogAnalyze the Verilog code for fast-page dram command.
Find the correct schematic - Urgent Memory Arbiter
VerilogAnalyze the Verilog code for urgent memory arbiter.
Complete the 5th SW→HW exercise
Find the correct schematic - Cache Write-policy Unit
VerilogAnalyze the Verilog code for cache write-policy unit.
Complete the 5th SW→HW exercise
Find the correct schematic - DMA Descriptor Address
VerilogAnalyze the Verilog code for dma descriptor address.
Complete the 5th SW→HW exercise
Find the correct schematic - Binary16 Floating-point Classifier
VerilogAnalyze the Verilog code for binary16 floating-point classifier.
Complete the 5th SW→HW exercise