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Testbench: Single-port RAM 256x8 (VHDL)

Validate

01

Objective

Verify synchronous writes and reads at several addresses. Use self-checking controls and finish with final_report.

02

Operation

Inputs: i_we (1 bit), i_addr (8 bits), i_din (8 bits). Outputs: o_dout (8 bits).

Behavior

Synchronous operations occur on the rising edge of i_clk. Allow signal updates to settle before comparing outputs.
256x8 memory initialized to zero at elaboration, without reset. Synchronous write at i_addr if i_we=1; synchronous read at i_addr. The post-edge output is the pre-edge contents (read-first), including read/write collisions.

Results

Ready to validate

Your testbench will run against the correct DUT and several hidden faults.

←Exercise list Next exerciseTestbench: Dual-port RAM 128x16→

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Beginner
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Progress

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Daily quests
Leaderboard

Testbench: Single-port RAM 256x8 (VHDL)

Validate

01

Objective

Verify synchronous writes and reads at several addresses. Use self-checking controls and finish with final_report.

02

Operation

Inputs: i_we (1 bit), i_addr (8 bits), i_din (8 bits). Outputs: o_dout (8 bits).

Behavior

Synchronous operations occur on the rising edge of i_clk. Allow signal updates to settle before comparing outputs.
256x8 memory initialized to zero at elaboration, without reset. Synchronous write at i_addr if i_we=1; synchronous read at i_addr. The post-edge output is the pre-edge contents (read-first), including read/write collisions.

Results

Ready to validate

Your testbench will run against the correct DUT and several hidden faults.

←Exercise list Next exerciseTestbench: Dual-port RAM 128x16→

Advanced