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SystemVerilog is used here to verify Verilog circuits. The design under test (DUT) is provided: write a testbench with stimulus and self-checking assertions.
0/40 exercises completed
AND gate testbench
SystemVerilogWrite a self-checking testbench that covers the complete truth table of an AND gate.
2-to-1 multiplexer testbench
SystemVerilogAutomatically verify both data paths and both selector values.
4-bit counter testbench
SystemVerilogBuild a clock and verify asynchronous reset, enable, counting and wrap-around.
Testbench: OR gate
SystemVerilogVerify all four rows of an OR gate truth table.
Testbench: XOR gate
SystemVerilogVerify the truth table and both cases where exactly one input is active.
Testbench: Inverter gate
SystemVerilogVerify that the output is inverted for both input values.
Complete Testbench: XOR gate
Testbench: NAND gate
SystemVerilogVerify the negated product, especially the two-input-high case.
Complete Testbench: Inverter gate
Testbench: NOR gate
SystemVerilogVerify the low output when an input is active and the high idle output.
Complete Testbench: NAND gate
Testbench: 2-to-4 decoder
SystemVerilogVerify one-hot decoding and the enable behavior.
Complete Testbench: NOR gate
Testbench: 4-bit comparator
SystemVerilogVerify less-than, equal and greater-than relations on representative values.
Complete Testbench: 2-to-4 decoder
Testbench: 4-bit parity generator
SystemVerilogVerify even parity for zero, an odd value and a two-bit value.
Complete Testbench: 4-bit comparator
Testbench: Half adder
SystemVerilogVerify sum and carry for all four input pairs.
Complete Testbench: 4-bit parity generator
Testbench: 1-bit full adder
SystemVerilogVerify sum and carry with and without an input carry.
Complete Testbench: Half adder
Testbench: 4-bit adder
SystemVerilogVerify carries, zero operands and addition overflow.
Complete Testbench: 1-bit full adder
Testbench: 4-bit subtractor
SystemVerilogVerify difference and borrow for subtractions with and without borrow.
Complete Testbench: 4-bit adder
Testbench: 4-bit priority encoder
SystemVerilogVerify most-significant-bit priority and the no-request case.
Complete Testbench: 4-bit subtractor
Testbench: 7-segment decoder
SystemVerilogVerify digits 0, 1, 8 and an out-of-range value.
Complete Testbench: 4-bit priority encoder
Testbench: 4-bit shifter
SystemVerilogVerify left and right shifts with discarded outgoing bits.
Complete Testbench: 7-segment decoder
Testbench: 4-bit enabled register
SystemVerilogVerify asynchronous reset, capture and hold while enable is disabled.
Complete Testbench: 4-bit shifter
Testbench: Serial shift register
SystemVerilogVerify serial insertion and bit progression across several edges.
Complete Testbench: 4-bit enabled register
Testbench: Rising-edge detector
SystemVerilogVerify that a one-cycle pulse appears only on a rising transition.
Complete Testbench: Serial shift register
Testbench: Enabled D flip-flop
SystemVerilogVerify rising-edge capture and hold when enable is low.
Complete Testbench: Rising-edge detector
Testbench: 4-bit down counter
SystemVerilogVerify reset, hold and wrap-around from zero to fifteen.
Complete Testbench: Enabled D flip-flop
Testbench: Modulo-10 counter
SystemVerilogVerify the decimal sequence and return to zero after nine.
Complete Testbench: 4-bit down counter
Testbench: 4-bit ring counter
SystemVerilogVerify the active-bit rotation and cyclic return.
Complete Testbench: Modulo-10 counter
Testbench: 4-bit LFSR
SystemVerilogVerify the pseudo-random sequence and the non-zero state after reset.
Complete Testbench: 4-bit ring counter
Testbench: Pulse stretcher
SystemVerilogVerify that an input pulse produces the defined output duration.
Complete Testbench: 4-bit LFSR
Testbench: Debounce filter
SystemVerilogVerify that an input remains stable for several cycles before acceptance.
Complete Testbench: Pulse stretcher
Testbench: 4-bit PWM
SystemVerilogVerify duty-cycle boundaries and ramp transitions.
Complete Testbench: Debounce filter
Testbench: 4-bit timer
SystemVerilogVerify loading, countdown and the completion pulse.
Complete Testbench: 4-bit PWM
Testbench: Traffic-light FSM
SystemVerilogVerify cyclic state transitions and reset to the initial state.
Complete Testbench: 4-bit timer
Testbench: 101 sequence detector
SystemVerilogVerify overlapping detection and incomplete sequences.
Complete Testbench: Traffic-light FSM
Testbench: 4-bit accumulator
SystemVerilogVerify conditional addition, hold and modulo overflow.
Complete Testbench: 101 sequence detector
Testbench: 4-bit saturating adder
SystemVerilogVerify saturation at fifteen instead of wrap-around.
Complete Testbench: 4-bit accumulator
Testbench: Binary-to-Gray converter
SystemVerilogVerify zero, maximum and multi-bit transition values.
Complete Testbench: 4-bit saturating adder
Testbench: One-hot checker
SystemVerilogVerify zero, one active position and multiple active bits.
Complete Testbench: Binary-to-Gray converter
Testbench: 5-input majority voter
SystemVerilogVerify the four-to-one and three-to-two thresholds.
Complete Testbench: One-hot checker
Testbench: 8-bit parity generator
SystemVerilogVerify even, odd and extreme data words.
Complete Testbench: 5-input majority voter
Testbench: Register with priority clear
SystemVerilogVerify clear priority over writes and the hold behavior.
Complete Testbench: 8-bit parity generator
Testbench: Majority voter: symmetry
SystemVerilogVerify decisions on profiles close to the threshold.
Complete Testbench: Register with priority clear