Logic Gates

Fundamental logic gates: AND, OR, NOT, NAND, NOR, XOR and their properties.

Introduction to Digital Logic

Digital logic operates on two levels: 0 (false, low, GND) and 1 (true, high, VCC).

A logic gate is an electronic circuit that performs a logical operation on one or more input bits to produce one output bit.

Real Logic Levels

A 0 and a 1 are not magic values: they are voltage ranges recognized by components.

In common positive logic:

• 0 is a low voltage, close to GND;
• 1 is a high voltage, close to VCC;
• between them, there is an uncertain region to avoid.

A component does not switch exactly at VCC / 2. It has input thresholds: below one level, the signal is read as 0; above another level, it is read as 1. The gap between the produced signal and the required threshold is the noise margin.

Noise, Load and Delays

A digital signal can be disturbed by noise, bouncing, coupling between traces or poor supply decoupling. Digital logic tolerates these imperfections better than analog circuits, but it does not make them disappear.

Three ideas matter:

• fan-out: how many inputs one output can drive correctly;
• propagation delay: time between an input change and a stable output;
• non-ideal edge: a real transition takes finite time and may be noisy.

On an FPGA, you do not directly choose a discrete gate family, but these effects still exist in I/O buffers, LUTs, routing and timing constraints.

TTL and CMOS as Background

Historically, many logic circuits used TTL (transistor-transistor logic) with a typical 5 V supply. Modern circuits mostly use CMOS, which is more power-efficient and available at many voltages: 3.3 V, 2.5 V, 1.8 V, and others.

The point is not to memorize every logic family, but to understand that an interface must respect:

• voltages accepted by the input;
• voltages produced by the output;
• available current;
• time required for the signal to become stable.

A digital signal is still a real electrical signal. It can be clean, noisy, too slow, overloaded or incompatible with the next input.

Fundamental Gates

NOT (Inverter)

o_y <= NOT i_a;

AND

o_y <= i_a AND i_b;

OR

o_y <= i_a OR i_b;

Derived Gates

NAND (NOT AND)

The universal gate - any logic function can be built using only NAND gates.

o_y <= i_a NAND i_b;

NOR (NOT OR)

Also universal.

o_y <= i_a NOR i_b;

XOR (Exclusive OR)

Outputs 1 only when the inputs are different.

o_y <= i_a XOR i_b;

Common use: parity detection, 1-bit adder (sum).

XNOR (Exclusive NOR)

Outputs 1 when inputs are identical (1-bit comparator).

o_y <= i_a XNOR i_b;

Equivalences

Implementation on FPGA

On FPGAs, logic gates are not discrete physical components - they are implemented inside LUTs.

A LUT-6 can implement any combination of logic gates on up to 6 inputs. The synthesizer decides how to map your logical expression onto available LUTs.

-- This complex expression probably fits in 1 LUT
o_y <= (i_a AND i_b) OR (i_c XOR i_d) OR (NOT i_e);

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