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Logic Gates

Name: Logic Gates
Author: Dangremont Jayson

By Dangremont JaysonAbout the author (in French)

Fundamental logic gates: AND, OR, NOT, NAND, NOR, XOR and their properties.

A gate takes one or more input bits and produces one result bit. Those bits correspond to voltage ranges: in positive logic, a low level represents 0 and a high level represents 1.

Connect bits to electrical signals

The low level is near and the high level near . Between the input thresholds lies an undefined region to avoid. A device therefore does not necessarily switch at . Noise margin is the room between the generated level and the required threshold.

GND

VCC

VCC / 2

Noise, contact bounce, trace coupling and poor decoupling can disturb a signal. Logic ranges tolerate some disturbances, but you must still check:

fan-out: how many inputs the output can drive correctly;
propagation delay from an input change to a settled output;
edge transition time, which is finite in a real circuit.

Older TTL (transistor-transistor logic) families often used 5 V. CMOS now dominates, generally consumes less power and is available at voltages including 3.3 V, 2.5 V and 1.8 V. An interface must meet input and output voltage requirements, available current and settling time. On an FPGA, these constraints affect I/O buffers, LUTs and routing.

Read the gate functions

Invert with NOT

The output is the complement of the input.

A	Y
0	1
1	0

o_y <= NOT i_a;

Combine with AND and OR

AND produces 1 when all inputs are 1.

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

o_y <= i_a AND i_b;

OR produces 1 when at least one input is 1.

A	B	Y
0	0	0
0	1	1
1	0	1
1	1	1

o_y <= i_a OR i_b;

Invert the result: NAND and NOR

NAND inverts AND. It is universal: a network of NAND gates can implement any logic function.

A	B	Y = NOT(A AND B)
0	0	1
0	1	1
1	0	1
1	1	0

o_y <= i_a NAND i_b;

NOR inverts OR and has the same universal property.

A	B	Y = NOT(A OR B)
0	0	1
0	1	0
1	0	0
1	1	0

o_y <= i_a NOR i_b;

Compare two bits: XOR and XNOR

XOR produces 1 when the two inputs differ. Common uses include parity and the sum output of a one-bit adder.

A	B	Y
0	0	0
0	1	1
1	0	1
1	1	0

o_y <= i_a XOR i_b;

XNOR produces 1 when the inputs match, providing a one-bit equality comparison.

A	B	Y
0	0	1
0	1	0
1	0	0
1	1	1

o_y <= i_a XNOR i_b;

The next table connects symbols with equivalent expressions.

Gate	NAND Equivalent	NOR Equivalent
NOT A	NAND(A, A)	NOR(A, A)
A AND B	NAND(NAND(A,B), NAND(A,B))	-
A OR B	-	NOR(NOR(A,B), NOR(A,B))

Implement the function on an FPGA

The synthesizer maps logic expressions into available LUTs. A six-input LUT can implement any Boolean function of up to six inputs, so several written gates do not necessarily require separate physical elements.

-- This complex expression probably fits in 1 LUT
o_y <= (i_a AND i_b) OR (i_c XOR i_d) OR (NOT i_e);

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