Combinational Design

Move from a logic requirement to a truth table, a simplified expression and a VHDL implementation.

What combinational logic does

A combinational circuit produces an output that depends only on its current inputs. It stores no state. When inputs change, signals propagate through gates, then the output stabilizes after a finite delay.

Classic examples:

• multiplexer;
• decoder;
• comparator;
• adder;
• flag computation;
• bus selection logic.

The design method is the same for a small circuit and for a more realistic VHDL block.

Design method

1. Define the inputs and outputs precisely.
2. Write the truth table or the useful cases.
3. Derive a logic expression.
4. Simplify if it clarifies the circuit.
5. Write the VHDL.
6. Simulate the important cases.

On an FPGA, the synthesizer already simplifies many expressions. Manual simplification is mostly useful for understanding, documentation and avoiding ambiguous cases.

Example: majority detector

The output Y must be 1 if at least two inputs among A, B, C are 1.

Sum-of-products expression:

Y = A·B + A·C + B·C

VHDL implementation:

o_y <= (i_a AND i_b) OR
       (i_a AND i_c) OR
       (i_b AND i_c);

This expression maps to three simple conditions: each input pair can activate the output.

Multiplexer

A multiplexer selects one input among several. For a 2-to-1 MUX:

Expression:

Y = (NOT SEL AND A) OR (SEL AND B)

Readable VHDL:

o_y <= i_b when i_sel = '1' else i_a;

Conditional style is usually clearer than a gate expression when the intent is selection.

Decoder

A decoder activates one output according to an input value. Example: decode two bits into four lines.

with i_sel select
  o_y <= "0001" when "00",
         "0010" when "01",
         "0100" when "10",
         "1000" when others;

This block is common for selecting a register, generating enables or building a simple interface.

Don't-care conditions

Some input combinations may never occur. These are often called don't cares. They can help simplify a function, but they must be used carefully.

Example: a valid BCD digit goes from 0000 to 1001. Values 1010 to 1111 may be considered invalid if the circuit guarantees they never occur.

Good practice:

• use don't cares for reasoning;
• write defined VHDL behavior for every value;
• verify invalid values in simulation.

with i_bcd select
  o_valid <= '1' when "0000" | "0001" | "0010" | "0011" | "0100" |
                      "0101" | "0110" | "0111" | "1000" | "1001",
             '0' when others;

Watch for unintended latches

In a combinational process, each output must receive a value on every path. Otherwise, the synthesizer may infer unwanted memory.

process(all)
begin
  o_y <= '0';
 
  if i_enable = '1' then
    o_y <= i_a AND i_b;
  end if;
end process;

The default value makes the behavior complete and avoids an implicit dependency on the previous value of o_y.

Key points

• A truth table turns a logic requirement into verifiable cases.
• A gate expression should be readable, not only minimal.
• Multiplexers, decoders and comparators are common combinational building blocks.
• In combinational VHDL, covering every case avoids unintended memory.

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