Writing a condition with AND, OR and NOT lets you transform it without changing its result. George Boole published this algebra in 1854; Claude Shannon applied it to circuits in 1937.
Transform an expression
In these equations, · means AND, + means OR and means complement. They represent logical operations rather than ordinary arithmetic.
¬
Basic identities provide the first simplifications:
Theorem
AND
OR
Identity
A · 1 = A
A + 0 = A
Null
A · 0 = 0
A + 1 = 1
Idempotence
A · A = A
A + A = A
Complement
A · Ā = 0
A + Ā = 1
Involution
¬(¬A) = A
Commutativity changes operand order, while associativity changes grouping:
A · B = B · A A + B = B + A(A · B) · C = A · (B · C) (A + B) + C = A + (B + C)
Distributivity connects logical sums and products:
A · (B + C) = (A · B) + (A · C)A + (B · C) = (A + B) · (A + C)
De Morgan's laws move an inversion by exchanging AND and OR. They are particularly useful when reasoning about NAND and NOR networks:
¬(A · B) = ¬A + ¬B (NOT AND = OR of complements)¬(A + B) = ¬A · ¬B (NOT OR = AND of complements)
In VHDL, they produce these equivalent expressions:
-- De Morgan 1: NOT (A AND B) = (NOT A) OR (NOT B)o_y <= NOT (i_a AND i_b); -- equivalent to:o_y <= (NOT i_a) OR (NOT i_b);-- De Morgan 2: NOT (A OR B) = (NOT A) AND (NOT B)o_y <= NOT (i_a OR i_b); -- equivalent to:o_y <= (NOT i_a) AND (NOT i_b);
Apply the rules step by step so the simplification remains easy to check:
F = A·B + A·B̄ = A·(B + B̄) (distributivity) = A·1 (complement) = A (identity)
See the grouping with Karnaugh maps
A Karnaugh map is convenient for two to four variables. This is the two-variable arrangement:
B=0
B=1
A=0
F(0,0)
F(0,1)
A=1
F(1,0)
F(1,1)
For F(A,B,C) = Σ(1,3,5,7), all four cells set to 1 correspond to C = 1:
AB=00
AB=01
AB=11
AB=10
C=0
0
0
0
0
C=1
1
1
1
1
Their group therefore gives F = C. Form rectangular groups of 2ⁿ cells: 1, 2, 4, 8 and so on. Groups may overlap and wrap across opposite edges. Larger groups eliminate more variables from the resulting term.
Connect the truth table to VHDL
In sum-of-products form (SOP), each minterm corresponds to a row with output 1:
F = A·B·C̄ + A·B̄·C + Ā·B·C
In product-of-sums form (POS), each maxterm corresponds to a row with output 0:
F = (A+B+C̄) · (A+B̄+C) · (Ā+B+C)
These forms translate directly into VHDL expressions:
-- Unsimplified expressiono_f <= (i_a AND i_b AND NOT i_c) OR (i_a AND NOT i_b AND i_c) OR (NOT i_a AND i_b AND i_c);-- The synthesizer automatically simplifies!-- You do NOT need to simplify manually for synthesis.-- The synthesizer uses its own algorithms (ESPRESSO, etc.)
The synthesizer already simplifies logic. Manual work mainly helps you understand the function and resulting circuit, and makes the code easier to review.