AXI4 Master — Write Channels

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01General Operation

AXI4 single-beat write master. The rising edge of i_write_go triggers a transaction. The three channels AW (address), W (data), and B (response) operate independently with VALID/READY handshake. WLAST='1' always (single-beat).

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_rst`	Input	1 bit	Synchronous reset
`i_write_go`	Input	1 bit	Write trigger
`i_wr_addr`	Input	32 bits	Write address
`i_wdata`	Input	32 bits	Write data
`o_wr_done`	Output	1 bit	Write done pulse (1 cycle)
`m_axi_awaddr`	Output	32 bits	AXI Write Address
`m_axi_awvalid`	Output	1 bit	AXI AW Valid
`m_axi_awready`	Input	1 bit	AXI AW Ready
`m_axi_wdata`	Output	32 bits	AXI Write Data
`m_axi_wstrb`	Output	4 bits	AXI Write Strobe
`m_axi_wlast`	Output	1 bit	AXI Write Last
`m_axi_wvalid`	Output	1 bit	AXI W Valid
`m_axi_wready`	Input	1 bit	AXI W Ready
`m_axi_bresp`	Input	2 bits	AXI Write Response
`m_axi_bvalid`	Input	1 bit	AXI B Valid
`m_axi_bready`	Output	1 bit	AXI B Ready

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