Chargement…
Chargement…
mu0 is an accumulator-based 16-bit processor with:
io_data (16b) and io_addr (12b), plus o_memrq / o_rnw for RAM dialogueEach instruction takes 2 clock cycles (one FETCH + one EXECUTE).
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | Clock |
i_reset | Input | 1 bit | Active-high asynchronous reset |
io_data | In/Out | 16 bits | Bidirectional data bus |
io_addr | In/Out | 12 bits | Bidirectional address bus |
o_memrq | Output | 1 bit | Memory request (1 = memory access) |
o_rnw | Output | 1 bit | 1 = read, 0 = write |
Each instruction word: IR[15:12] = opcode, IR[11:0] = addr.
| Mnemonic | Opcode | Action |
|---|---|---|
LDA addr | 0000 | ACC <- mem[addr] |
STO addr | 0001 | mem[addr] <- ACC |
ADD addr | 0010 | ACC <- ACC + mem[addr] |
SUB addr | 0011 | ACC <- ACC - mem[addr] |
JMP addr | 0100 | PC <- addr |
JGE addr | 0101 | if ACC(15)='0' then PC <- addr |
JNE addr | 0110 | if ACC /= 0 then PC <- addr |
STP | 0111 | Halt the CPU |
AND addr | 1000 | ACC <- ACC and mem[addr] |
OR addr | 1001 | ACC <- ACC or mem[addr] |
XOR addr | 1010 | ACC <- ACC xor mem[addr] |
LDR addr | 1011 | R <- addr (immediate load) |
LDI | 1100 | ACC <- mem[R] ; R <- R+1 |
STI | 1101 | mem[R] <- ACC ; R <- R+1 |
The sequencer drives the following control signals:
o_selA (2 bits): address bus io_addr source - "00" -> pc_out (FETCH default)
- "01" -> r_out (LDI / STI indirect)
- "10" -> unused (zero)
- "11" -> ir_addr (direct addressing)
o_selB (1 bit): ALU B input - '0' -> "0000" & io_addr (zero-extended addr, used by jumps and PC/R increments)
- '1' -> io_data (memory read for LDA/ADD/SUB/AND/OR/XOR)
o_selC (1 bit): ACC load source - '0' -> ALU output
- '1' -> io_data (LDI)
o_acc_ld, o_pc_ld, o_r_ld, o_ir_ld: register load enableso_acc_oe: enables ACC tristate on io_data (STO / STI)o_alufs: ALU operationo_memrq, o_rnw: memory control (rnw='1' = read)Four states: INIT, FETCH, EXECUTE, STOP.
o_raz='1', move to FETCH on next cycle.selA="00" (PC), selB='0', alufs=ALU_B_INC, ir_ld='1', pc_ld='1'. Move to EXECUTE.Combinational default values: o_selA="00", o_selB='0', o_selC='0', all ld to '0', o_acc_oe='0', o_alufs=ALU_B_INC, o_memrq='1', o_rnw='1'.
The (provided) RAM contains a 30-instruction program covering all 14 opcodes. After the program completes, the testbench checks 9 memory cells (mem[0x30]..mem[0x38]) - one per tested path: arithmetic chains (LDA+ADD+STO, SUB+AND+OR+XOR+STO), taken/not-taken branches of JGE and JNE, JMP, indirect addressing (LDR+LDI+STO), and two consecutive STI writes to validate R post-increment.