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Memory Arbiter

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Specification

01General Operation

The circuit is combinational. Master 0 has priority over master 1.

Behaviour

If i_m0_req=1, the memory port receives master 0 signals.
Otherwise, if i_m1_req=1, it receives master 1 signals.
i_mem_ready and i_mem_rdata are returned only to the granted master.

02Interface

Signal	Direction	Width	Description
`i_m0_req`	Input	1 bit	Master 0 request
`i_m0_we`	Input	1 bit	Master 0 write enable
`i_m0_addr`	Input	8 bits	Master 0 address
`i_m0_wdata`	Input	8 bits	Master 0 write data
`i_m1_req`	Input	1 bit	Master 1 request
`i_m1_we`	Input	1 bit	Master 1 write enable
`i_m1_addr`	Input	8 bits	Master 1 address
`i_m1_wdata`	Input	8 bits	Master 1 write data
`i_mem_ready`	Input	1 bit	Memory ready
`i_mem_rdata`	Input	8 bits	Memory read data
`o_mem_valid`	Output	1 bit	Valid memory request
`o_mem_we`	Output	1 bit	Memory write enable
`o_mem_addr`	Output	8 bits	Memory address
`o_mem_wdata`	Output	8 bits	Memory write data
`o_m0_ready`	Output	1 bit	Master 0 ready response
`o_m0_rdata`	Output	8 bits	Master 0 read data
`o_m1_ready`	Output	1 bit	Master 1 ready response
`o_m1_rdata`	Output	8 bits	Master 1 read data

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