Fixed-Point Sequential Neuron

The block computes ReLU(bias + sum(value_k * weight_k)) over a sequence of signed 8-bit pairs. The bias is signed 16-bit.

Required datapath

• one signed 8 by 8-bit multiplier;
• sign extension of the 16-bit product;
• one signed 24-bit accumulator;
• an 8-bit saturating ReLU activation.

The output is 0 when the final sum is negative or zero, the sum when it is between 1 and 127, and 127 above that. This exercise performs inference only. Weights are supplied by the upstream block and are not trained in the FPGA.

Behaviour

• i_start is accepted while o_ready='1'. That edge loads i_bias and starts a new sum.
• i_value and i_weight pairs are consumed only when i_valid='1'. They start no earlier than the cycle after i_start.
• i_last='1' marks the final pair and is considered only together with i_valid='1'.
• The final product is included in the sum before activation.
• o_done pulses for one cycle with o_value.
• Bubbles where i_valid='0' do not change the accumulator.
• An active-high asynchronous reset cancels the operation in progress.