SPI Slave (CPOL=0, CPHA=0)
BeginnerSign in →
00:00
01General Operation
The module implements an SPI slave in mode 0 (CPOL=0, CPHA=0). Data is sampled on the rising edge of SCLK. When Slave Select is active (low), the slave receives 32 bits serially on MOSI and presents them in parallel on the output. A signal indicates reception completion.
Reset is asynchronous and active-low.
- SCLK signal must be resynchronized into the system clock domain
- Bit counter and register are reset when SS_N is inactive
02Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset_n | Input | 1 bit | Active-low async reset |
i_sclk | Input | 1 bit | SPI clock (external domain) |
i_ss_n | Input | 1 bit | Active-low Slave Select |
i_MOSI | Input | 1 bit | Master Out Slave In |
o_r_data | Output | 32 bits | Received data |
o_top | Output | 1 bit | Data valid pulse (1 sys cycle) |