SPI Slave (CPOL=0, CPHA=1)

Beginner

00:00

Specification

01General Operation

The module implements an SPI slave in mode 1 (CPOL=0, CPHA=1). Data is sampled on the falling edge of i_sclk. While i_ss_n is active low, the slave receives 32 serial bits on i_MOSI. The received frame and its completion indicator are then transferred into the i_clk domain through two synchronization stages.

i_reset_n is active low: it asynchronously resets SPI capture and is sampled on the rising edge of i_clk for the synchronization registers.

The SPI bit counter and shift register are also reset asynchronously while i_ss_n is inactive high
o_top is the completion indicator synchronized into the i_clk domain

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_reset_n`	Input	1 bit	Active-low reset: asynchronous in the SPI domain, synchronous in the `i_clk` domain
`i_sclk`	Input	1 bit	SPI clock (external domain)
`i_ss_n`	Input	1 bit	Active-low Slave Select
`i_MOSI`	Input	1 bit	Master Out Slave In
`o_r_data`	Output	32 bits	Synchronized received data
`o_top`	Output	1 bit	Synchronized completion indicator

← 4-Bit Ring Counter

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