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4-bit serial-in serial-out (SISO) shift register. On each rising clock edge, bits shift one position to the right: serial input enters at the MSB and the LSB exits through the serial output.
Reset is asynchronous and active-high.
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_sin | Input | 1 bit | Serial input |
o_sout | Output | 1 bit | Serial output (LSB) |
o_q | Output | 4 bits | Register content |