4-bit Shift Register

Beginner

00:00

01General Operation

4-bit serial-in serial-out (SISO) shift register. Bits move one position to the right on each clock cycle.

Behaviour:

Reset (i_reset='1'): o_q ← "0000", o_sout ← '0'.
Rising edge of i_clk: right shift, i_sin enters at the MSB, the LSB leaves through o_sout.
o_q continuously reflects the 4 flip-flop states.

*Asynchronous active-high reset.*

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_reset`	Input	1 bit	Active-high async reset
`i_sin`	Input	1 bit	Serial input
`o_sout`	Output	1 bit	Serial output (LSB)
`o_q`	Output	4 bits	Register content

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