Chargement…
Chargement…
The PWM generator produces a periodic signal whose duty cycle is controlled by i_duty. The signal period is set by the g_clk_hz and g_pwm_hz generics. The output is active when the internal counter is below the duty value.
Reset is asynchronous and active-high.
g_clk_hz (default 100,000,000) and g_pwm_hz (default 1,000)| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_duty | Input | 16 bits (unsigned) | Duty cycle |
o_pwm | Output | 1 bit | PWM signal |