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Chargement…
Purely structural top-level wiring two provided components:
Behaviour:
i_clk and i_reset, its enable is tied to '1'.o_seg directly.*No combinational logic to write: port map statements only.*
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
o_seg | Output | 7 bits | 7-seg segments |