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Chargement…
On rising edge of i_clk: if i_t = '1', the output toggles (r_q <= not r_q). If i_t = '0', the output is held. Asynchronous reset forces output to '0'.
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_t | Input | 1 bit | Toggle enable |
o_q | Output | 1 bit | Flip-flop output |