Chargement…
Chargement…
On rising edge of i_clk:
Asynchronous reset forces output to '0'.
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_s | Input | 1 bit | Set |
i_r | Input | 1 bit | Synchronous reset |
o_q | Output | 1 bit | Flip-flop output |