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On rising edge of i_clk, if i_en = '1', the value of i_d is stored. Asynchronous reset clears output to "0000".
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_en | Input | 1 bit | Enable |
i_d | Input | 4 bits | Data input |
o_q | Output | 4 bits | Stored data |