Chargement…
Chargement…
The module uses a simple valid/last stream.
Behaviour
i_clear clears the accumulator.i_valid=1 adds i_sample.i_last=1, o_sum includes the current sample and o_done pulses for one cycle.| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high asynchronous reset |
i_clear | Input | 1 bit | Internal clear |
i_valid | Input | 1 bit | Valid input sample |
i_last | Input | 1 bit | Last sample of the packet |
i_sample | Input | 8 bits | Input sample |
o_sum | Output | 12 bits | Output sum |
o_done | Output | 1 bit | Operation complete |