Chargement…
Chargement…
1. Request: when a new request arrives on the source side, data is latched and a request flag is raised. The module goes busy.
2. Request synchronization: the flag is synchronized into the destination domain via double flip-flop.
3. Acknowledgment: the destination domain signals reception. The ack is synchronized back to the source domain.
4. Release: upon receiving the ack, the request flag is lowered and the module becomes available.
Resets are synchronous in each respective domain.
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk_src | Input | 1 bit | Source clock domain |
i_clk_dest | Input | 1 bit | Destination clock domain |
i_rst_clk_src | Input | 1 bit | Synchronous reset source domain |
i_rst_clk_dest | Input | 1 bit | Synchronous reset destination domain |
i_new_request_clk_src | Input | 1 bit | New request (1 source cycle) |
o_busy_clk_src | Output | 1 bit | Transfer in progress |
i_data_clk_src | Input | 8 bits | Data to transfer |
o_new_data_clk_dest | Output | 1 bit | 1-cycle dest pulse: data valid |
o_data_clk_dest | Output | 8 bits | Received data |