TOP_LEVEL - BCD 7-Segment Counter

The schematic shows a TOP_LEVEL instantiating three provided components: a clock divider (generic g_divider => 100_000_000 for 1 Hz from 100 MHz), a BCD counter (0 to 9 with enable), and a 7-segment decoder (BCD to segment conversion, with enable). The w_clk_1hz signal generated by the divider must be connected to the bcd_counter i_en input; the counter i_clk_100Mhz remains connected to the TOP_LEVEL i_clk_100Mhz input. Use the provided package for the component ports and only edit top_level.vhd.

Useful course: VHDL chapter 14 - Components and instantiation.