library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.report_sim_pkg.all; entity tb_top_level is end entity; architecture sim of tb_top_level is -------------------------------------------------------------------------------- -- Constants -------------------------------------------------------------------------------- constant c_CLK_PERIOD : time := 10 ns; -------------------------------------------------------------------------------- -- Signals -------------------------------------------------------------------------------- signal s_clk : std_logic := '0'; signal s_reset : std_logic := '1'; signal s_hex : std_logic_vector(6 downto 0); signal s_seg_in : std_logic_vector(3 downto 0) := "0000"; signal s_seg_en : std_logic := '1'; signal s_seg_out : std_logic_vector(6 downto 0); signal s_bcd_en : std_logic := '0'; signal s_bcd_data : std_logic_vector(3 downto 0); component TOP_LEVEL is port ( i_clk_100Mhz : in std_logic; i_reset : in std_logic; o_hex : out std_logic_vector(6 downto 0) ); end component; component bcd_counter is port ( i_clk_100Mhz : in std_logic; i_reset : in std_logic; i_en : in std_logic; o_data : out std_logic_vector(3 downto 0) ); end component; component decodeur7seg is port ( i_en : in std_logic; i_data : in std_logic_vector(3 downto 0); o_hex : out std_logic_vector(6 downto 0) ); end component; begin s_clk <= not s_clk after c_CLK_PERIOD / 2; -------------------------------------------------------------------------------- -- Port Map -------------------------------------------------------------------------------- U_DUT : TOP_LEVEL port map ( i_clk_100Mhz => s_clk, i_reset => s_reset, o_hex => s_hex ); U_BCD : bcd_counter port map ( i_clk_100Mhz => s_clk, i_reset => s_reset, i_en => s_bcd_en, o_data => s_bcd_data ); U_SEG : decodeur7seg port map ( i_en => s_seg_en, i_data => s_seg_in, o_hex => s_seg_out ); -------------------------------------------------------------------------------- -- Stimulus -------------------------------------------------------------------------------- P_STIM : process variable v_pass : integer := 0; variable v_fail : integer := 0; variable v_tests : integer := 0; variable v_step : integer := 0; begin write_step(v_step, "decodeur7seg combinatorial"); s_seg_en <= '1'; s_seg_in <= "0000"; wait for 1 ns; check_output(s_seg_out, std_logic_vector'("1111110"), "seg digit 0", v_pass, v_fail, v_tests); s_seg_in <= "0001"; wait for 1 ns; check_output(s_seg_out, std_logic_vector'("0110000"), "seg digit 1", v_pass, v_fail, v_tests); s_seg_in <= "1001"; wait for 1 ns; check_output(s_seg_out, std_logic_vector'("1111011"), "seg digit 9", v_pass, v_fail, v_tests); s_seg_en <= '0'; wait for 1 ns; check_output(s_seg_out, std_logic_vector'("0000000"), "seg disabled", v_pass, v_fail, v_tests); s_seg_en <= '1'; write_step(v_step, "bcd_counter reset and count"); s_reset <= '1'; s_bcd_en <= '0'; wait for 5 * c_CLK_PERIOD; check_output(s_bcd_data, std_logic_vector'("0000"), "bcd after reset", v_pass, v_fail, v_tests); s_reset <= '0'; s_bcd_en <= '1'; for i in 0 to 9 loop wait for c_CLK_PERIOD; end loop; check_output(s_bcd_data, std_logic_vector'("0000"), "bcd after 10 counts", v_pass, v_fail, v_tests); write_step(v_step, "TOP_LEVEL integration after reset"); s_reset <= '1'; wait for 5 * c_CLK_PERIOD; s_reset <= '0'; wait for 10 * c_CLK_PERIOD; check_output(s_hex, std_logic_vector'("1111110"), "TOP_LEVEL hex after reset", v_pass, v_fail, v_tests); final_report("tb_top_level", v_pass, v_fail); wait; end process P_STIM; end architecture;

TOP_LEVEL — BCD 7-Segment Counter