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Burst DMA Controller

Advanced

Simulate (Icarus Verilog)

00:00

Specification

01Operation

Each word is read, buffered, and written before advancing both addresses.

Behavior

start loads addresses and word count while the DMA is idle.
rd_req remains asserted until rd_ack, then wr_req waits for wr_ack.
Addresses advance after each write; done pulses after the final word.

02Interface

Signal	Direction	Width	Description
`clk, reset, start`	Input	1 bit	Clock and start
`source_address, destination_address`	Input	16 bits	Initial addresses
`length`	Input	8 bits	Word count
`rd_req, rd_address`	Output	1/16 bits	Read request and address
`rd_ack, rd_data`	Input	1/16 bits	Read acknowledgement and data
`wr_req, wr_address, wr_data`	Output	1/16 bits	Write request, address, and data
`wr_ack`	Input	1 bit	Write acknowledgement
`busy, done`	Output	1 bit	Transfer status

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